Polysilicon gates prevent further improvement of the performance of metal oxide semiconductor (MOS) devices when the size of the devices is continuously reduced, due to the excessive large resistance of the gates, polysilicon depletion effect and boron penetration effect in PMOS transistors. Meanwhile, a serious interface defect is usually formed when integrating a polysilicon gate with a high K gate dielectric, which results in a pinning phenomenon of the device threshold and reduction in carrier mobility in channel. Therefore, a gate structure is put forward in which a metal gate is used to replace the polysilicon gate.
In an MOS device, the processes of integrating a metal gate/high K gate stack include a gate-first process and a gate-last process. In the gate-first process, a metal gate/high K gate stack is formed first, then the steps of source/drain regions implantation and activation annealing are performed. In the step of activation annealing of the source/drain regions, many materials of the metal gate react with the high K gate dielectric. Thus in the gate-first process, the materials of the metal gate are limited, which accordingly limits the increase of the threshold voltage of the device. In the gate-last process, a dummy gate (i.e. a sacrificial gate) of a polysilicon material, for example, is formed first, then the steps of source/drain regions implantation and activation annealing are performed, finally, the dummy gate is removed and a metal gate (i.e. a replacement gate) is formed. In the gate-last process, the material of the metal gate does not undergo the step of the activation annealing of the source/drain regions, and the processing temperature after forming the metal gate is usually under 500° C. By means of the gate-last process, more materials can be selected to form the metal gate so as to obtain the desired threshold voltage and to reduce the interface defect density of the metal gate/high K. Hence, the gate-last process has become an increasingly attractive option for integrating the metal gate.
In the gate-last process, the dummy gate needs to be covered by an interlayer dielectric layer (ILD) after its formation, then a smooth surface is formed on the ILD layer using Chemical Mechanical Polishing (CMP), afterwards, the dummy gate is removed and the opening formed thereby is filled with the material of the metal gate.
Moreover, the ILD layer also separates the metal wiring layer and the active layer of the semiconductor device, and the conductive via in the ILD layer is used to realize an electrical connection between the metal wiring and active regions of the semiconductor device. The ILD layer with a smooth surface can help the deposition and patterning of the metal gate material, help the electrical insulation between the metal wiring and the semiconductor device thereunder, and help formation of an interconnection of repeated metal wirings. Besides, the mechanical strength and reliability of the semiconductor device are improved thanks to the absence of such defect as cavity.
However, compared to the gate-first process, the gate-last process includes additional CMP processing in order to obtain an ILD layer with a smooth surface, thus increasing complexity of the manufacturing process and the cost, especially on the first isolation layer isolating the gate stack structure of a subminiature gate length. Besides, the CMP processing also has the following technical difficulties:                planarizing multiple materials (silicon oxide, silicon nitride, polysilicon) by CMP on the same platform        terminal monitoring of a super-thin isolation layer (about 100 nm in thickness with high uniformity)        new polishing liquid that is advanced and expensive has to be developed.        
A method of depositing conformal insulating layers, for example, a two-layered ILD layer structure of a low temperature oxide (LTO) layer and a spin coating glass (SOG) layer on the LTP layer, may be used to replace the CMP processing, wherein the LTO layer forms a conformal cover layer on a wafer of a large area, while the SOG layer further fills the dents of the surface profile, thus an approximately smooth surface is obtained.
Then, in order to further form a smooth surface, a dry etching, such as reactive ion etching, is used to back etch the SOG layer for planarization. In the reactive ion etching, a gas mixture of trifluoromethane (CHF3) and oxygen (O2) is usually used as the etching gas.
In the U.S. Pat. No. 5,316,980A by Shinichi Takeshiro, et. al., it is further provided that a gas mixture of trifluoromethane (CHF3) and hexafluoroethane (C2F6) is used as the etching gas, so that the rate of etching the organic SOG layer is lower than the rate of etching the underlying SiO2 layer, as a result, a smooth structural surface can still be obtained even if the underlying SiO2 is partially exposed.
However, the above-mentioned existing SOG layer etching method actually cannot obtain an overall smoothness. It has been found that during the etching, the rate of etching the SOG layer in the center of the wafer is lower than that in the edges of the wafer, and the section plane of the etched SOG layer is of a convex shape. As a result, the SOG layer at the edges of the wafer does not have the desired smoothness and has to be abandoned, thus the area of the wafer that can be used for manufacturing a semiconductor device is reduced. Moreover, there is a serious pattern effect during the overall planarizing process (i.e. pattern size and pattern density influence thick film etching rate).